1. Field of the Invention
The present invention relates to a scrambling apparatus, a descrambling apparatus, and methods thereof for performing a scrambling/descrambling process corresponding to M sequence with 16 bits in parallel.
2. Description of the Related Art
In a signal processing apparatus that processes a video signal in a digital format, for example, a digital VCR (Video Cassette Recorder) that records/reproduces a high resolution video signal, an input video signal is compression-encoded. The compression-encoded video signal is recorded to for example a video tape. To record/reproduce a video signal at high data rate, a helical scanning recording/reproducing apparatus is known. In the helical scanning recording/reproducing apparatus, the magnetic tape is diagonally wound on a rotating drum. Magnetic heads are disposed on the rotating drum. In this apparatus, data is successively recorded on the magnetic tape so that diagonal tracks are formed on the magnetic tape.
For example, data as a digital video signal is compression-encoded and then encoded with error correction code. The error-correction-code encoding process is often performed with for example product code. In this process, data of a matrix as symbols (for example, bytes) is encoded in the row direction with for example Reed Solomon code. Thus, an outer code parity is generated. In addition, the data and outer code parity are encoded in the line direction. Thus, an inner code parity is generated. In such a manner, with the outer code parity in the row direction and the inner code parity in the line direction, the error-correction-code encoding process is performed with product code. At this point, the time sequence of the data accords with for example the line direction.
Data for one line in the direction of the inner code is equivalent to one sync block. An error correction encoder that performs the error correction code encoding process adds an identification (ID) signal to each sync block.
The resultant data is recorded on the magnetic tape through an equalizer, a recording amplifier, and so forth. At this point, the data is recorded in the above-described helical scanning system. In addition, the data is recorded in azimuth system. In the azimuth system, with a set of recording magnetic heads that have different azimuth angles, data is recorded in such a manner that the azimuth angles of adjacent two tracks are different. A plurality of sync blocks are recorded on one track. Each track has a plurality of video sectors and a plurality of audio sectors.
A reproducing magnetic head reads data from the magnetic tape. Output data of the reproducing magnetic head is supplied to a reproducing amplifier and an equalizer. Thus, the resultant data is obtained as reproduced data. The reproduced data is supplied to an ECC (Error Correcting Code) decoder. The ECC decoder treats data of for example one sync block as one packet and decodes reproduced data corresponding to an ID designated to each packet.
The reproduced data is written to an RAM connected to the ECC decoder. The reproduced data is read in the direction of the inner code. Thus, an error of the reproduced data is corrected with the inner code (this process is referred to as inner code error correcting process). Next, to correct an error of the reproduced data with the outer code (this process is referred to as outer code error correcting process), the reproduced data that has been corrected with the inner code is rewritten to the RAM. In the RAM, the reproduced data is written as packets to addresses corresponding to IDs designated to the packets.
The reproduced data written to the RAM is read in the order of addresses. Thus, errors of the packets are corrected with the outer code. At this point, there may be a packet whose error has not been corrected with the inner code. In this case, the ID of the packet is unreliable. Thus, a packet cannot be written to a correct address of the RAM. Thus, the error of the packet may not be corrected with the outer code.
To solve such a problem, after performing the inner code error correcting process for each packet, the ECC decoder reproduces an ID thereof. For example, the ECC decoder predicts the ID of the packet that has an error with reference to adjacent packets thereof and replaces the ID of the error packet with the predicted ID. Thus, a packet that has been determined as an error packet in the inner code error correcting process can be correctly used in the outer code error correcting process.
The resultant data is rewritten to the RAM. The data that has been written to the RAM is read in the direction of the inner code. Thus, data in the time sequence is obtained. Data that is output from the ECC decoder is decompressed.
In such a digital VCR, to disperse the deviation of the record frequency of successive "0s" and "1s" and repetitive pattern data, when a signal is recorded, it is scrambled. Thus, the distribution of the record frequency is flattened. In the scrambling process, random numbers referred to as M sequence is used. The M sequence is generated by a circuit equivalent to the following primitive polynomial. EQU X.sup.8 +X.sup.4 +X.sup.3 +X.sup.2 +1 (1)
When such data is reproduced, it should be descrambled. The descrambling process is preceded by the inter code correcting process. FIG. 1 is a block diagram showing a circuit that generates random numbers of the M sequence corresponding to Formula (1) and performs the descrambling process. The circuit equivalent to Formula (1) is composed of a plurality of flip-flops 200a to 200h and a plurality of Ex-OR gates 201a to 201c.
The flip-flop 200a serially outputs random numbers of the M sequence. The random numbers of the M sequence that are output from the flip-flop 200a are supplied to one input terminal of the Ex-OR gate 202. Serial data to be descrambled is supplied to the other input terminal of the Ex-OR gate 202. The Ex-OR gate 202 Ex-ORs the serial data and the random numbers of the M sequence and outputs descrambled data.
The descrambling process and the scrambling process can be accomplished by the same structure.
In the structure shown in FIG. 1, since data is processed at data rate of serial data, the operation frequency becomes high. To suppress the operation frequency from becoming high, the descrambling process is performed with eight bits in parallel by a circuit (shown in FIG. 2A) equivalent to a generated polynomial given by FIG. 2B. In the circuit shown in FIG. 2A, each connection line has a data width of a plurality of bits. Ex-OR gates 210a to 210h have respective input terminals. The circuit shown in FIG. 2A generates a fixed pattern that is output from the flip-flop 200a shown in FIG. 1 eight times at a time. In this case, the scrambling process and the descrambling process are performed by the same circuit. The start position of the M sequence is supplied to an input terminal 211. The output data of an output terminal 212 and data to be descrambled are ex-ORed.
In the circuit shown in FIG. 2A, the data width is eight bits. Thus, this circuit cannot be applied for a unit that operates with data of 16 bits wide. When the data width is converted from 16 bits to eight bits, the circuit shown in FIG. 2A can be used. However, since the data rate is doubled, it may be difficult from a viewpoint of process speed.